The recent advancement in high-performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. By encapsulating the die with a molding compound and leaving the die top exposed (chip with face-down or die-down configuration), this package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. Methods to improve heat dissipation in the die-down package configuration are desired.
Several U.S. patents discuss thermal interface materials, including U.S. Pat. No. 10,083,939 (Seo et al), U.S. Pat. No. 8,310,067 (Zhao et al), and U.S. Pat. No. 10,008,475 (Chiu) and U.S. Patent Application 2014/0368992 (Strader et al). Some other patents discuss heat dissipation methods, including U.S. Pat. No. 7,221,055 (Lange) and U.S. Patent Applications 2017/0345744 (Olsen), 2016/0268190 (Mcknight-MacNeil et al), 2016/0247742 (Vadhavkar et al), and 2016/0035645 (Olsen et al). Other patents teach die attach methods, including U.S. Pat. No. 5,319,242 (Carney et al) and U.S. Patent Application 2013/0062760 (Hung et al).